1. Field of the Invention
The present invention relates to a semiconductor memory device, and, more particularly, to a novel structure of a dynamic random access memory (DRAM) with a hierarchical bit line structure.
2. Description of the Related Art
DRAMs are very popular as a fast access memory with a large capacity for use as a CPU s cache memory. To ensure an ever-increasing capacity, the size of memory cells should be made smaller. This structure increases the number of memory cells to be connected to a single bit line and expanding the capacity of bit lines. In existing DRAMs which store data of 1 or 0 by the presence or absence of charges, reducing the size of memory cells and increasing the bit line capacity make smaller a minute voltage to be read on a bit line and makes the sensing of sense amplifiers difficult. Further, an increase in the load capacity of bit lines increases the power dissipation that is caused by driving the bit lines.
As a solution to this shortcoming has been proposed a hierarchical bit structure in which each bit line consists of a global bit line and a plurality of local bit lines connectable to the global bit line. In this structure, memory cells are located at intersections of word lines and local bit lines and those local bit lines which correspond to a selected word line are connected to the associated global bit lines. This reduces the entire capacity of the bit lines to be connected to sense amplifiers. Further, the provision of a plurality of local bit lines in parallel to each global bit line can secure sufficient pitches between the global bit lines and also secure sufficient space for the sense amplifiers that are connected to the global bit lines. This can ensure high integration.
There is a known semiconductor memory device of a folded bit line type in which pairs of bit lines to be connected to sense amplifiers are laid out in parallel. This bit line system is known to be unsusceptible to noise on the bit lines at the time of reading data. It is expected that the use of the above-described hierarchical bit line structure in the folded bit line system provides a noise unsusceptible structure with a larger capacity.
The use of the hierarchical bit line structure in the folded bit line system however allows only a single memory cell to be laid along a word line with respect to two sets of a plurality of local bit lines, each set provided in parallel to a single global bit line and connected to a sense amplifier. This is because that the folded bit line system requires that a memory cell should be laid on one of a pair of global bit lines along a word line. Therefore, the employment of the hierarchical bit line structure in the folded bit line system is not a preferable choice from the viewpoint of the layout efficiency of memory cells.
It is thus desirable from the viewpoint of the layout efficiency of memory cells to use the hierarchical bit line structure in an open bit line system. The present inventor has proposed a similar memory in a Japanese patent application filed on Mar. 4, 1996 and later laid open as Unexamined Japanese Patent Publication No. Hei 8-45712.
The open bit line system however has a problem on noise of bit lines which occurs in the amplifying operation of sense amplifiers at the time of reading data. When most of the bit lines laid on one side of the sense amplifiers read, for example, "0" and a very few read "1," the potentials of most bit lines are set to an L level simultaneously in accordance with the amplifying operation of the sense amplifiers. This causes the very few bit lines that are reading "1" to be influenced by L-level noise.
Any memory, which employs a hierarchical bit line structure in order to increase the margin for sense amplifiers to meet significant capacity expansion, should avoid this noise problem. As has been discussed above, it is difficult to realize a memory which is unsusceptible to noise on bit lines at the time of data reading while maintaining the area efficiency of memory cells to ensure huge capacity.
Accordingly, it is an object of the present invention to provide a semiconductor memory device which is suitable for accomplishing vast capacity with less dissipation power and is capable of ensuring a large operational margin in read mode.
It is another object of this invention to provide a semiconductor memory device with a hierarchical bit line structure which can ensure a large operational margin in read mode.